R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 131

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
4.4
This is a reset generated by the RES pin.
When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a
reset state. In order to firmly reset the LSI, the STBY pin should be set to high and the RES pin
should be held low at least for 20 ms at a power-on. During operation, the RES pin should be held
low at least for 20 states.
4.5
This is an internal reset generated by the power-on reset circuit.
If RES is in the high-level state when power is supplied, a power-on reset is generated. After Vcc
has exceeded Vpor and the specified period (power-on reset time) has elapsed, the chip is released
from the power-on reset state. The power-on reset time is a period for stabilization of the external
power supply and the LSI circuit.
If RES is at the high-level when the power-supply voltage (Vcc) falls to or below Vpor, a power-
on reset is generated. The chip is released after Vcc has risen above Vpor and the power-on reset
time has elapsed.
After a power-on reset has been generated, the PORF bit in RSTSR is set to 1. The PORF bit is in
a read-only register and is only initialized by a pin reset. Figure 4.2 shows the operation of a
power-on reset.
Pin Reset
Power-on Reset (POR) (H8SX/1665M Group)
Rev. 2.00 Oct. 21, 2009 Page 97 of 1454
REJ09B0498-0200
Section 4 Resets

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