R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 20

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 12 Data Transfer Controller (DTC)...................................................... 555
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
Rev. 2.00 Oct. 21, 2009 Page xviii of xxxii
Features............................................................................................................................. 555
Register Descriptions........................................................................................................ 557
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.2.9
Activation Sources............................................................................................................ 565
Location of Transfer Information and DTC Vector Table................................................ 566
Operation .......................................................................................................................... 571
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.5.6
12.5.7
12.5.8
12.5.9
12.5.10 DTC Bus Release Timing ................................................................................. 584
12.5.11 DTC Priority Level Control to the CPU ........................................................... 584
DTC Activation by Interrupt............................................................................................. 585
Examples of Use of the DTC............................................................................................ 586
12.7.1
12.7.2
12.7.3
Interrupt Sources............................................................................................................... 589
Usage Notes ...................................................................................................................... 589
12.9.1
12.9.2
12.9.3
12.9.4
12.9.5
12.9.6
Transfer Information Start Address, Source Address, and Destination
Address ............................................................................................................. 590
DTC Mode Register A (MRA) ......................................................................... 558
DTC Mode Register B (MRB).......................................................................... 559
DTC Source Address Register (SAR)............................................................... 560
DTC Destination Address Register (DAR)....................................................... 561
DTC Transfer Count Register A (CRA) ........................................................... 561
DTC Transfer Count Register B (CRB)............................................................ 562
DTC enable registers A to F (DTCERA to DTCERF) ..................................... 562
DTC Control Register (DTCCR) ...................................................................... 563
DTC Vector Base Register (DTCVBR)............................................................ 565
Bus Cycle Division ........................................................................................... 573
Transfer Information Read Skip Function ........................................................ 575
Transfer Information Writeback Skip Function................................................ 576
Normal Transfer Mode ..................................................................................... 576
Repeat Transfer Mode ...................................................................................... 577
Block Transfer Mode ........................................................................................ 579
Chain Transfer .................................................................................................. 580
Operation Timing.............................................................................................. 581
Number of DTC Execution Cycles ................................................................... 583
Normal Transfer Mode ..................................................................................... 586
Chain Transfer .................................................................................................. 586
Chain Transfer when Counter = 0..................................................................... 587
Module Stop State Setting ................................................................................ 589
On-Chip RAM .................................................................................................. 589
DMAC Transfer End Interrupt.......................................................................... 589
DTCE Bit Setting.............................................................................................. 589
Chain Transfer .................................................................................................. 590