R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 963

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.6.4
Figure 19.21 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 19.22 shows a sample flowchart
for serial data reception.
or output, starts receiving data, and stores the receive data in RSR.
is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF
flag remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
Figure 19.21 Example of Operation for Reception in Clocked Synchronous Mode
Synchronization
clock
Serial data
RDRF
ORER
Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)
RXI interrupt
request
generated
Bit 7
Bit 0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
1 frame
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Bit 7
Bit 0
RXI interrupt
request generated
Rev. 2.00 Oct. 21, 2009 Page 929 of 1454
Bit 1
ERI interrupt request
generated by overrun
error
Bit 6
Bit 7
REJ09B0498-0200