R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 264

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
(d) Address/data multiplexed I/O interface
The number of access cycles in data cycle of the address/data multiplexed I/O interface is the
same as that in the basic bus interface. The number of access cycles in address cycle can be
specified as two or three cycles by the ADDEX bit in MPXCR.
(e)
In the DRAM interface, the numbers of precharge cycles, row address output cycles, and column
address output cycles can be specified.
The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in
DRACCR. The number of row address output cycles can be specified as one to four cycles by bits
RCD1 and RCD0 in DRACCR. The number of column address output cycles can be specified as
two or three cycles by the CAST bit in DRAMCR. For the column address output cycle, program
wait (0 to 7 cycles) specified by WTCRB or external wait by WAIT can be inserted.
(f)
In the SDRAM interface, the numbers of precharge cycles, row address output cycles, and column
address output cycles, as well as clock suspend and write-precharge delay, can be specified by
DRACCR and WTCRB.
The number of precharge cycles can be specified as one to four cycles by bits TPC1 and TPC0 in
DRACCR. The number of row address output cycles can be specified as one to four cycles by bits
RCD1 and RCD0 in DRACCR. The number of column address output cycles during read access
can be specified as two to four cycles by bits W21 and W20 in WTCRB.
The cycles for clock suspend and write-precharge delay can be inserted by bits CKSPE and
TRWL in SDCR.
Rev. 2.00 Oct. 21, 2009 Page 230 of 1454
REJ09B0498-0200
DRAM Interface
SDRAM Interface
Number of access cycles in the address/data multiplexed I/O interface
= number of address output cycles (2, 3) + number of data output cycles (2, 3)
Number of access cycles in the DRAM interface
= number of precharge cycles (1 to 4) + number of row address output cycles (1 to 4)
+ number of program wait cycles (0 to 7)
+ number of CS extension cycles (0, 1, 2)
[+number of external wait cycles by the WAIT pin]
+ number of column address output cycles (2 or 3)
+ number of program wait cycles (0 to 7)
[+number of external wait cycles by the WAIT pin]