R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 951

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

No
No
Read receive data in RDR, and
clear RDRF flag in SSR to 0
PER ∨ FER ∨ ORER = 1
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Read ORER, PER, and
Figure 19.12 Sample Serial Reception Flowchart (1)
All data received?
FER flags in SSR
Start reception
Initialization
RDRF = 1
<End>
Yes
Yes
No
(Continued on next page)
Error processing
Yes
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] [3] Receive error processing and break
[4] SCI state check and receive data read:
[5] Serial reception continuation procedure:
The RxD pin is automatically
designated as the receive data input
pin.
detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag and RDR,
and clear the RDRF flag to 0.
However, the RDRF flag is cleared
automatically when the DMAC or DTC
is initiated by an RXI interrupt and
reads data from RDR.
Rev. 2.00 Oct. 21, 2009 Page 917 of 1454
REJ09B0498-0200