R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 580

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 11 EXDMA Controller (EXDMAC)
(6)
If an NMI interrupt occurs, the EXDMAC clears the DTE bit to 0 in all channels and sets the
ERRF bit in EDMDR_0 to 1. EXDMA transfer is aborted when an NMI interrupt is generated
during EXDMA transfer. To perform EXDMA transfer after an NMI interrupt occurs, clear the
ERRF bit to 0 and then set the DTE bit to 1 in all channels.
The following explains the transfer end timing in each mode after an NMI interrupt is detected.
(a)
In dual address mode, EXDMA transfer ends at the end of the EXDMA transfer write cycle in
units of transfers.
In single address mode, EXDMA transfer ends at the end of the EXDMA transfer bus cycle in
units of transfers.
(b) Block transfer mode
A block size EXDMA transfer is aborted. A block size transfer is not correctly executed, thus
matching between the actual transfer and the transfer request is not guaranteed.
In dual address mode, a write cycle corresponding to a read cycle is executed as well as in the
normal transfer mode.
(c)
A cluster size EXDMA transfer is aborted. If transfer is aborted in a read cycle, the read data is not
guaranteed. If transfer is aborted in a write cycle, the data not transferred is not guaranteed.
Matching between the transfer counter and the address register is not guaranteed since the transfer
processing cannot be controlled.
(7)
If an address error occurs, the EXDMAC clears the DTE bit to 0 in all channels, and set the ERRF
bit in EDMDR_0 to 1. An address error during EXDMA transfer forcibly terminates the transfer.
To perform EXDMA transfer after an address error occurs, clear the ERRF bit to 0 and then set
the DTE bit to 1 in each channel.
The transfer end timing after address error detection is the same as for the one when an NMI
interrupt occurs.
Rev. 2.00 Oct. 21, 2009 Page 546 of 1454
REJ09B0498-0200
Transfer End by NMI Interrupt
Normal transfer mode and repeat transfer mode
Cluster transfer mode
Transfer End by Address Error