R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 542

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 11 EXDMA Controller (EXDMAC)
(5)
Figure 11.31 shows an example of normal transfer mode transfer activated by the EDREQ pin low
level.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes
and EDREQ pin low level sampling is performed again. This sequence of operations is repeated
until the end of the transfer.
Rev. 2.00 Oct. 21, 2009 Page 508 of 1454
REJ09B0498-0200
EDREQ
Address
bus
EXDMA
control
Channel
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of Bφ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] EXDMA cycle starts.
[4], [7] Acceptance is resumed after completion of write cycle.
(As in [1], EDREQ pin low level is sampled at rise of Bφ, and request is held.)
EDREQ Pin Low Level Activation Timing
Figure 11.31 Example of Normal Transfer Mode Transfer Activated
[1]
Request
Minimum 3 cycles
Idle
Bus release
[2]
Read
[3]
Duration of transfer
EXDMA read EXDMA write
request disabled
Transfer
source
Write
by EDREQ Pin Low Level
Transfer request enable resumed
destination
Transfer
[4]
Idle
Request
Minimum 3 cycles
Bus release
[5]
Read
[6]
EXDMA read EXDMA write
Duration of transfer
request disabled
Transfer
source
Write
Transfer request enable resumed
destination
Transfer
Idle
[7]
Bus release

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