R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1125

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
22.4.5
In system clock mode, set Iφ = 50 MHz, Pφ = Iφ/2, and make the sampling setting 25. A/D
conversion*
the frequency of the system clock relative to the input clock, see section 27, Clock Pulse
Generator.
When the ADST bit is cleared to 0, start A/D conversion following the procedures shown below.
1. Set Pφ = Iφ/2.
2. Release the A/D converter from the module-stopped state.
3. Set the EXCKS*
4. Set*
5. Write H'19 to ADSSTR*
6. Start A/D conversion (set the ADST bit to 1 or have the trigger signal initiate conversion).
Notes: 1. The full-spec emulator (E6000H) should not be used, but the on-chip emulator (E10A-
ADTRG0
ADST
Internal trigger
signal
Figure 22.8 External Trigger Input Timing when Multiple Units Start Simultaneously
ADSSTR*
2. For unit 0, the full-spec emulator (E6000H) should not be used, but the on-chip
3. For unit 1, access to the full-spec emulator (E6000H) is prohibited, but the on-chip
2
*
3
Setting the System Clock Mode
the ICKSEL bit in ADMODSEL*
USB) is usable.
emulator (E10A-USB) is usable.
emulator (E10A-USB) is usable.
1
with a conversion time of 1 µs per channel is possible. For information on controlling
2
*
3
effective).
2
bit in ADCSR to 1 (making setting of the number of states for sampling in
(TRSG1, TRGS0, and EXTRGS = B'111)
2
*
3
(setting the number of states for sampling to 25).
2
*
3
to 1 (selecting system clock mode).
Rev. 2.00 Oct. 21, 2009 Page 1091 of 1454
Section 22 A/D Converter
REJ09B0498-0200
A/D conversion

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