R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 339

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.11.5
Figures 9.60 and 9.61 show a basic access timing of the SDRAM space.
A basic read cycle consists of five clock cycles: one precharge cycle (Tp), one row address output
cycle (Tr), and three column address output cycles (Tc1, Tcl, and Tc2).
A basic write cycle consists of four clock cycles: one precharge cycle (Tp), one row address
output cycle (Tr), and two column address output cycles (Tc1 and Tc2).
When the SDRAM space is selected, the WAITE bit in BCR, the RAST and CAST bits in
DRAMCR, bits RCW1 and RCW0 in REFCR are ignored.
Basic Timing
Figure 9.60 SDRAM Basic Read Access Timing (CAS Latency = 2)
Precharge-sel
Address bus
D15 to D8
SDRAMφ
D7 to D0
DQMLU
DQMLL
RD/WR
RAS
CAS
CKE
WE
CS
BS
PALL
T p
Row address
ACTV
address
Row
T r
READ
T c1
Column address
Rev. 2.00 Oct. 21, 2009 Page 305 of 1454
T cl
NOP
Section 9 Bus Controller (BSC)
T c2
REJ09B0498-0200