R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1117

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
1. Set the ADSTCLR bit in ADCR to 1.
2. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR (units 2 and 3), or an
3. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
4. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
5. The ADST bit is automatically cleared when A/D conversion is completed for all of the
ADST
ADF
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
ADDRA
ADDRB
ADDRC
ADDRD
external trigger input, A/D conversion starts on the first channel in the specified channel group.
Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10)
can be selected. For unit 1, A/D conversion starts on AN4 when CH3 and CH2 = B'01.
transferred to the corresponding ADDR of each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated.
channels that have been selected. A/D conversion stops and the A/D converter enters a wait
state.
One-Cycle Scan Mode*
Notes: 1.
2.
(Continuous Scan Mode, Three Channels (AN0 to AN2) Selected)
↓ indicates the timing of instruction execution by software.
Data being converted is ignored.
Waiting for
conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
Figure 22.4 Example of A/D Conversion
Set *
A/D
conver-
sion 1
1
Transfer
A/D conversion consecutive execution
A/D
conver-
sion 2
Waiting for conversion
A/D conversion result 1
A/D
conver-
sion 3
Waiting for conversion
Rev. 2.00 Oct. 21, 2009 Page 1083 of 1454
A/D conversion time
A/D
conver-
sion 4
A/D conversion result 2
A/D conversion result 3
A/D
conver-
sion 5
Section 22 A/D Converter
A/D conversion result 4
Waiting for conversion
Waiting for conversion
*
Clear *
2
REJ09B0498-0200
Waiting for
conversion
1
Clear *
1