R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 482

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
10.9
1. DMAC Register Access During Operation
2. Settings of Module Stop Function
3. Activation by DREQ Falling Edge
4. Acceptation of Activation Source
Rev. 2.00 Oct. 21, 2009 Page 448 of 1454
REJ09B0498-0200
Except for clearing the DTE bit in DMDR, the settings for channels being transferred
(including waiting state) must not be changed. The register settings must be changed during
the transfer prohibited state.
The DMAC operation can be enabled or disabled by the module stop control register. The
DMAC is enabled by the initial value.
Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC
enters the module stop state. However, when a transfer for a channel is enabled or when an
interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the
DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13.
When the clock is stopped, the DMAC registers cannot be accessed. However, the following
register settings are valid in the module stop state. Disable them before entering the module
stop state, if necessary.
⎯ TENDE bit in DMDR is 1 (the TEND signal output enabled)
⎯ DACKE bit in DMDR is 1 (the DACK signal output enabled)
The DREQ falling edge detection is synchronized with the DMAC internal operation.
A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to
B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made.
C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is
After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is
sampled by low level detection at the first activation after a DMAC transfer enabled.
At the beginning of an activation source reception, a low level is detected regardless of the
setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven
low before setting DMDR, the low level is received as a transfer request.
When the DMAC is activated, clear the DREQ signal of the previous transfer.
2. is made.
made.
Usage Notes