R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 345

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.11.8
When the time between the PALL or PRE command and the subsequent ACTV or REF command
does not meet a given specification, the Tp cycles can be extended by one to four cycles by bits
TPC1 and TPC0 in DRACCR. Set the bit according to the SDRAM to be used and the frequency
of this LSI so that the number of Tp cycles can be optimal.
Figures 9.65 and 9.66 show a timing example when the two Tp cycles are inserted.
Bits TPC1 and TPC0 are effective for the Tp cycle in a refresh cycle.
Controlling Precharge Cycle
Figure 9.65 Read Timing Example of Two Precharge Cycles
Precharge-sel
Address bus
D15 to D8
SDRAMφ
D7 to D0
DQMLU
DQMLL
RD/WR
RAS
CAS
CKE
WE
CS
BS
(TPC1 = 0, TPC0 = 1, CAS Latency = 2)
PALL
T
p1
Row address
NOP
T
p2
address
Row
ACTV
T
r
READ
High
T
c1
Column address
Rev. 2.00 Oct. 21, 2009 Page 311 of 1454
T
cl
NOP
Section 9 Bus Controller (BSC)
T
c2
REJ09B0498-0200

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