R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 247

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
10
9
8
7
6
5
4
Bit Name
RTCK2
RTCK1
RTCK0
RFSHE
RLW2
RLW1
RLW0
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Refresh Counter Clock Select
Select the clock used to count up the refresh counter
from the seven internal clocks generated by dividing the
on-chip peripheral module clock (Pφ). When the clock is
selected, the refresh counter starts to count up.
000: Counting halted
001: Counts on Pφ/2
001: Counts on Pφ/8
001: Counts on Pφ/32
001: Counts on Pφ/128
001: Counts on Pφ/512
001: Counts on Pφ/2048
001: Counts on Pφ/4096
Refresh Control
Enables or disables refresh control. When refresh
control is disabled, the refresh timer can be used as the
interval timer.
In single-chip activation mode, the setting of this bit
should be made after setting the EXPE bit in SYSCR to
1. For SYSCR, see section 3, MCU Operating Modes.
0: Refresh control enabled
1: Refresh control disabled
Refresh Cycle Wait Control
Select the number of wait cycles during a CAS before
RAS refresh cycle for the DRAM interface and an auto-
refresh cycle for the SDRAM interface.
000: No wait cycle inserted
001: One wait cycle inserted
010: Two wait cycles inserted
010: Three wait cycles inserted
010: Four wait cycles inserted
010: Five wait cycles inserted
010: Six wait cycles inserted
010: Seven wait cycles inserted
Rev. 2.00 Oct. 21, 2009 Page 213 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200