R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 257

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Name
Output enable/clock enable
SDRAMφ
Wait
Bus request
Bus request acknowledge
Bus request output
Data transfer acknowledge 3
(DMAC_3)
Data transfer acknowledge 2
(DMAC_2
Data transfer acknowledge 1
(DMAC_1)
Data transfer acknowledge 0
(DMAC_0)
Data transfer acknowledge 3
(EXDMAC_3)
Data transfer acknowledge 2
(EXDMAC_2
Data transfer acknowledge 1
(EXDMAC_1)
Data transfer acknowledge 0
(EXDMAC_0)
External bus clock
Symbol
OE/CKE
SDRAMφ
WAIT
BREQ
BACK
BREQO
DACK3
DACK2
DACK1
DACK0
EDACK3
EDACK2
EDACK1
EDACK0
I/O
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Function
SDRAM dedicated clock
Wait request signal when accessing external address
space
Request signal for release of bus to external bus
master
Acknowledge signal indicating that bus has been
released to external bus master
External bus request signal used when internal bus
master accesses external address space in the
external-bus released state
Data acknowledge signal for DMAC_3 single address
transfer
Data acknowledge signal for DMAC_2 single address
transfer
Data acknowledge signal for DMAC_1 single address
transfer
Data acknowledge signal for DMAC_0 single address
transfer
Data acknowledge signal for EXDMAC_3 single
address transfer
Data acknowledge signal for EXDMAC_2 single
address transfer
Data acknowledge signal for EXDMAC_1 single
address transfer
Data acknowledge signal for EXDMAC_0 single
address transfer
External bus clock
Output enable signal for DRAM
Clock enable signal for SDRAM
Rev. 2.00 Oct. 21, 2009 Page 223 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200

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