R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 147

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.3.2
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
6.3.3
After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF,
respectively, and all modules except the DTC, DMAC, and EXDMAC enter the module stop state.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when the module stop state is canceled.
Interrupts after Reset
On-Chip Peripheral Functions after Reset Release
Figure 6.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)
(1): Reset exception handling vector address (when reset, (1) = H'000000)
(2): Start address (contents of reset exception handling vector address)
(3) Start address ((3) = (2))
(4) First instruction in the exception handling routine
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
I φ
RES
Vector
fetch
(1)
(2)
Rev. 2.00 Oct. 21, 2009 Page 113 of 1454
operation
Internal
High
instruction
prefetch
Section 6 Exception Handling
First
(3)
(4)
REJ09B0498-0200

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