R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 965

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 19.23 Sample Flowchart of Simultaneous Serial Transmission and Reception
Note: When switching from transmit or receive operation to
No
No
No
simultaneous transmit and receive operations, first clear
the TE bit and RE bit to 0, then set both these bits to 1
simultaneously.
Clear TE and RE bits in SCR to 0
Write transmit data to TDR and
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Start transmission/reception
clear TDRE flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
All data received?
Initialization
ORER = 1
RDRF = 1
TDRE = 1
<End>
Yes
Yes
Yes
No
Error processing
Yes
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] SCI state check and transmit data
[3] Receive error processing:
[4] SCI state check and receive data
[5] Serial transmission/reception
Rev. 2.00 Oct. 21, 2009 Page 931 of 1454
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0. Transition of the
TDRE flag from 0 to 1 can also be
identified by a TXI interrupt.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to
0. Reception cannot be resumed if
the ORER flag is set to 1.
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
However, the TDRE flag is checked
and cleared automatically when the
DMAC or DTC is initiated by a
transmit data empty interrupt (TXI)
request and writes data to TDR.
Similarly, the RDRF flag is cleared
automatically when the DMAC or
DTC is initiated by a receive data
full interrupt (RXI) and reads data
from RDR.
REJ09B0498-0200