R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 423

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note:
Bit
2
1
0
*
Bit Name
DMAP2
DMAP1
DMAP0
Only 0 can be written to, to clear the flag.
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
DMA Priority Level 2 to 0
Select the priority level of the DMAC when using the
CPU priority control function over DMAC. When the
CPU has priority over the DMAC, the DMAC masks a
transfer request and waits for the timing when the CPU
priority becomes lower than the DMAC priority. The
priority levels can be set to the individual channels. This
bit is valid when the CPUPCE bit in CPUPCR is set to 1.
000: Priority level 0 (low)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (high)
Rev. 2.00 Oct. 21, 2009 Page 389 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200

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