R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 998

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 USB Function Module (USB)
20.3.1
IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared.
Rev. 2.00 Oct. 21, 2009 Page 964 of 1454
REJ09B0498-0200
Bit
7
6
5
Bit
Bit Name
Initial Value
R/W
Bit Name
BRST
EP1 FULL
EP2 TR
Interrupt Flag Register 0 (IFR0)
BRST
R/W
7
0
EP1 FULL
Initial
Value
0
0
0
R
6
0
R/W
R/W
R
R/W
EP2 TR
R/W
5
0
Description
Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
EP1 FIFO Full
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1
as long as there is valid data in the FIFO buffer.
This is a status bit, and cannot be cleared.
EP2 Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 2 is received from
the host. A NACK handshake is returned to the host until
data is written to the FIFO buffer and packet
transmission is enabled.
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure to
read the flag after writing 0 to it.)
EP2 EMPTY
R
4
1
SETUP TS
R/W
3
0
EP0o TS
R/W
2
0
EP0i TR
R/W
1
0
EP0i TS
R/W
0
0