R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 363

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(b) Self-Refresh in Deep Software Standby Mode
The chip passes through the software standby mode in transitions to deep software standby mode.
The states of pins in software standby mode are retained in the deep software standby mode.
Therefore, the transition to self-refreshing is possible in deep software standby mode as well as in
software standby mode.
In deep software standby mode, initiate the transition to the self-refresh after having set the
IOKEEP bit in DPSBYCR to 1 as well as making the setting in "(a) Self-Refresh in Software
Standby Mode ".
On exit from deep software standby mode, use the following procedure to cancel self-refresh. (See
figure 9.81).
1. In PBDDR/PBDR, set PB1 (CS2) as a high-level output and PB5 (CKE) as a low-level
2. Set the PSTOP0 bit in SCKCR to1 and SDRAMφ as a high level output. Since the setting
3. Clear the IOKEEP bit in DPSBYCR.
4. In the synchronous DRAM-related control registers that were initialized by the internal
5. Restart output of the SDRAMφ clock signal by clearing the PSTOP0 bit in SCKCR. This
6.
7. Resume access to the synchronous DRAM.
output.
Since the setting of the IOKEEP bit ensures retention of pin state at this time, the existing
state of high-level output on CS2 and low-level output on is retained.
of the IOKEEP bit continues to ensure retention of pin state, the existing state of high-
level output on SDRAMφ is retained.
This releases pin states from retention due to the setting of the IOKEEP bit, but the states
of pins CS2, CKE, and SDRAMφ as set in steps 1and 2 do not change.
reset that accompanied the transition to deep software standby mode, remake the settings
to enable the synchronous DRAM interface. At this time, do not make settings in REFCR,
RTCNT, and RTCOR.
Once the synchronous DRAM interface has been enabled, the state of the CKE pin
changes from low-level output to high-level output.
restarts supply of SDRAMφ to the synchronous DRAM.
As the state of the CKE pin has been changed in the step 4, adjust the time between the
state of change of the CKE pin and the next cycle of auto-refreshing in this procedure
within the stipulated refreshing interval of the synchronous DRAM.
Pre-charging time after the termination of self-refresh will be secured by the timing of the
setting in step 6.
Set REFCR, RTCNT, and RTCOR and enable refreshing.
Rev. 2.00 Oct. 21, 2009 Page 329 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200