R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 563

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The cluster size is decremented regardless of the read or write operation in the consecutive write
sequences.
(2)
In this mode, the transfer source address is specified in the source address register (EDSAR) and
data is read from the transfer source and transferred to the cluster buffer. In this mode, the TSEIE
bit in the mode control register (EDMDR) must be set to 1.
Two data access size to 32 bytes can be specified as a cluster size for the consecutive read
operation.
The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another
bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer.
ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND
is output for the last read cycle. When an idle cycle is inserted before the last read cycle, the
ETEND signal is also output in the idle cycle.
In this mode, the EDACKE bit in EDMDR must be set to 0 to disable the EDACK pin output.
Figure 11.57 shows the data flow in the cluster transfer read address mode (from the external
memory to the cluster buffer), and figure 11.58 shows an example of the timing in cluster transfer
read address mode.
H'AA0000
H'AA0004
H'AA0008
H'AA000C
H'AA0010
Cluster Transfer Read Address Mode (AMS = 1, DIRS = 0)
MSB
Transfer source memory
Word
Long Word
Long Word
Long Word
5
Byte
Byte
2
3
4
1
6
LSB
Figure 11.56 Odd Address Transfer
CLSBR0
CLSBR1
CLSBR2
CLSBR3
CLSBR4
CLSBR5
CLSBR6
CLSBR7
Cluster buffer
1
4
2
3
5
2
3
4
6
Rev. 2.00 Oct. 21, 2009 Page 529 of 1454
Section 11 EXDMA Controller (EXDMAC)
H'BB0000
H'BB0004
H'BB0008
H'BB000C
H'BB0010
Transfer destination memory
Word
REJ09B0498-0200
Long Word
Long Word
Long Word
Word