R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 214

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 9 Bus Controller (BSC)
• DRAM interface
• Synchronous DRAM interface
• Idle cycle insertion
• Write buffer function
• External bus release function
• Bus arbitration function
• EXDMAC external bus transfers and internal accesses can be executed in parallel.
• Multi-clock function
• The bus start (BS) and read/write (RD/WR) signals can be output.
Rev. 2.00 Oct. 21, 2009 Page 180 of 1454
REJ09B0498-0200
DRAM interface is available as area 2
Row/column address-multiplexed output (8, 9, 10, or 11 bits)
Two CAS signals control byte accesses for 16-bit data bus device
CAS assertion period can be extended by a program wait and a pin wait
Burst access can be performed in fast page mode
Tp cycle for ensuring a RAS precharge time can be inserted
CAS-before-RAS refresh (CBR refresh) and self refresh are selectable
Synchronous DRAM interface is available as area 2
Row/column address-multiplexed output (8, 9, 10, or 11 bits)
DQM signals control byte access for 16-bit data bus device
Auto refresh and self refresh are selectable
CAS latency can be selected from 2 to 4
High-speed data transfer is available using EXDMAC cluster transfer
Idle cycles can be inserted between external read accesses to different areas
Idle cycles can be inserted before the external write access after an external read access
Idle cycles can be inserted before the external read access after an external write access
Idle cycles can be inserted before the external access after a DMAC/EXDMAC single address
transfer (write access)
External write cycles and internal accesses can be executed in parallel
Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed
in parallel
DMAC single address transfers and internal accesses can be executed in parallel
Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, EXDMAC,
DTC, refresh cycle, and external bus master
The internal peripheral functions can be operated in synchronization with the peripheral
module clock (Pφ). Accesses to the external address space can be operated in synchronization
with the external bus clock (Bφ).

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