R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 619

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.6
The procedure for using the DTC with interrupt activation is shown in figure 12.15.
Clear corresponding
bit in DTCER
information in DTC vector table
Set starts address of transfer
Clear RRS bit in DTCCR to 0
Corresponding bit in DTCER
request for activation source
DTC Activation by Interrupt
Interrupt request generated
Set RRS bit in DTCCR to 1
DTC activation by interrupt
(MRA, MRB, SAR, DAR,
Set enable bit of interrupt
Set corresponding bit in
cleared or CPU interrupt
Set transfer information
clearing method of
activation source
DTC activated
Transfer end
DTCER to 1
CRA, CRB)
Determine
requested
to 1
Figure 12.15 DTC with Interrupt Activation
Clear
activation
source
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Clearing the RRS bit in DTCCR to 0 clears the read skip flag
of transfer information. Read skip is not performed when the
DTC is activated after clearing the RRS bit. When updating
transfer information, the RRS bit must be cleared.
Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer
information in the data area. For details on setting transfer
information, see section 12.2, Register Descriptions. For details
on location of transfer information, see section 12.4, Location of
Transfer Information and DTC Vector Table.
Set the start address of the transfer information in the DTC
vector table. For details on setting DTC vector table, see section
12.4, Location of Transfer Information and DTC Vector Table.
Setting the RRS bit to 1 performs a read skip of second time or
later transfer information when the DTC is activated consecu-
tively by the same interrupt source. Setting the RRS bit to 1 is
always allowed. However, the value set during transfer will be
valid from the next transfer.
Set the bit in DTCER corresponding to the DTC activation
interrupt source to 1. For the correspondence of interrupts and
DTCER, refer to table 12.1. The bit in DTCER may be set to 1 on
the second or later transfer. In this case, setting the bit is not
needed.
Set the enable bits for the interrupt sources to be used as the
activation sources to 1. The DTC is activated when an interrupt
used as an activation source is generated. For details on the
settings of the interrupt enable bits, see the corresponding
descriptions of the corresponding module.
After the end of one data transfer, the DTC clears the activation
source flag or clears the corresponding bit in DTCER and
requests an interrupt to the CPU. The operation after transfer
depends on the transfer information. For details, see section
12.2, Register Descriptions and figure 12.4.
Section 12 Data Transfer Controller (DTC)
Rev. 2.00 Oct. 21, 2009 Page 585 of 1454
REJ09B0498-0200