R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1275

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.6
27.6.1
1. The following points should be noted since the frequency of φ (Iφ: system clock, Pφ:
2. All the on-chip peripheral modules (except for the EXDMAC, DMAC, and DTC) operate on
3. The relationship among the system clock, peripheral module clock, and external bus clock is Iφ
4. Note that the frequency of φ will be changed in the middle of a bus cycle when setting SCKCR
5. Figure 27.9 shows the clock modification timing. After a value is written to SCKCR, this LSI
peripheral module clock, Bφ: external bus clock) supplied to each module changes according
to the setting of SCKCR.
Select a clock division ratio that is within the operation guaranteed range of clock cycle time
t
Since If min = 8MHz, Pf min = 8MHz, Bf min = 8MHz,
I f max = 50 MHz, P f max = 35 MHz, and Bf max = 50 MHz,
the frequencies should satisfy the conditions 8 MHz £ If £ 50 MHz, 8 MHz £ Pf £ 35 MHz,
and 8 MHz £ Bf £ 50 MHz.
the Pφ. Note therefore that the time processing of modules such as a timer and SCI differs
before and after changing the clock division ratio.
In addition, wait time for clearing software standby mode differs by changing the clock
division ratio. For details, see section 28.7.3, Setting Oscillation Settling Time after Exit from
Software Standby Mode.
≥ Pφ and Iφ ≥ Bφ. In addition, the system clock setting has the highest priority. Accordingly,
Pφ or Bφ may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits
PCK2 to PCK0 or BCK2 to BCK0.f
or SUBCKCR while executing the external bus cycle with the write-data-buffer function and
EXDMAC.
waits for the current bus cycle to complete. After the current bus cycle completes, each clock
frequency will be modified within one cycle (worst case) of the external input clock φ.
cyc
shown in the AC timing of electrical characteristics.
Usage Notes
Notes on Clock Pulse Generator
Rev. 2.00 Oct. 21, 2009 Page 1241 of 1454
Section 27 Clock Pulse Generator
REJ09B0498-0200