R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 239

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
11
10
9
8
7
Bit Name
OEE
RAST
CAST
BE
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
Description
OE Output Enable
The OE signal is output when DRAM with the EDO
page mode is connected, whereas the CKE signal is
output when SDRAM is connected.
0: OE/CKE signal output disabled (the OE/CKE pin can
1: OE/CKE signal enabled
RAS Assertion Timing Select
Selects whether the RAS signal is asserted at the rising
edge or falling edge of the Bφ signal in the Tr cycle
during a DRAM access. The relationship between this
bit and RAS assertion timing is shown in figure 9.4.
When SDRAM is used, the setting of this bit does not
affect operation.
0: RAS signal is asserted at the falling edge of the Bf
1: RAS signal is asserted at the rising edge of the Bf
Reserved
The initial value should not be changed.
Column Address Output Cycle Count Select
Selects whether the number of column address output
cycles is two or three during a DRAM access.
When SDRAM is used, the setting of this bit does not
affect operation.
0: Column address is output for two cycles
1: Column address is output for three cycles
Burst Access Enable
Enables or disables a burst access to the
DRAM/SDRAM. The DRAM/SDRAM is accessed in
high-speed page mode. When DRAM with the EDO
page mode is used, connect the OE signal of this LSI to
the OE signal of DRAM.
0: DRAM/SDRAM is accessed with full access
1: DRAM/SDRAM is accessed in high-speed page
be used as an I/O port)
signal in the Tr cycle
signal in the Tr cycle
mode
Rev. 2.00 Oct. 21, 2009 Page 205 of 1454
Section 9 Bus Controller (BSC)
REJ09B0498-0200

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