R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 476

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
(6)
When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the
ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the
transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the
ERRF bit to 0 and then set the DTE bits for the channels to 1.
The transfer end timings after an NMI interrupt is requested are shown below.
(a)
In dual address mode, a DMA transfer is completed after completion of the write cycle for one
transfer unit.
In single address mode, a DMA transfer is completed after completion of the bus cycle for one
transfer unit.
(b) Block Transfer Mode
A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is
not guaranteed.
In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar
in normal transfer mode.
(7)
When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit
in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is
forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0
and then set the DTE bits for the channels.
The transfer end timing after an address error is the same as that after an NMI interrupt.
(8)
The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA
transfer is not guaranteed.
Rev. 2.00 Oct. 21, 2009 Page 442 of 1454
REJ09B0498-0200
Transfer End by NMI Interrupt
Normal Transfer Mode and Repeat Transfer Mode
Transfer End by Address Error
Transfer End by Hardware Standby Mode or Reset