R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 817

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• NDRH_1
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3 to 0
Bit
7 to 4
3
2
1
0
If pulse output groups 6 and 7 have the same output trigger, all eight bits are mapped to the
same address and can be accessed at one time, as shown below.
If pulse output groups 6 and 7 have different output triggers, the upper four bits and lower four
bits are mapped to different addresses as shown below.
Bit Name
NDR31
NDR30
NDR29
NDR28
NDR27
NDR26
NDR25
NDR24
Bit Name
NDR31
NDR30
NDR29
NDR28
Bit Name
NDR27
NDR26
NDR25
NDR24
Initial
Value
0
0
0
0
0
0
0
0
Initial
Value
0
0
0
0
All 1
Initial
Value
All 1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Next Data Register 31 to 24
The register contents are transferred to the
corresponding PODRH_1 bits by the output trigger
specified with PCR_1.
Description
Next Data Register 31 to 28
The register contents are transferred to the
corresponding PODRH_1 bits by the output trigger
specified with PCR_1.
Reserved
These bits are always read as 1 and cannot be modified.
Description
Reserved
These bits are always read as 1 and cannot be modified.
Next Data Register 27 to 24
The register contents are transferred to the
corresponding PODRH_1 bits by the output trigger
specified with PCR_1.
Section 15 Programmable Pulse Generator (PPG)
Rev. 2.00 Oct. 21, 2009 Page 783 of 1454
REJ09B0498-0200

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