R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1015

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.3.20 FIFO Clear Register (FCLR)
FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the
data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.
Do not clear a FIFO buffer during transfer.
Bit
7
6
5
4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Bit Name
⎯
EP3 CLR
EP1 CLR
EP2 CLR
⎯
⎯
EP0o CLR
EP0i CLR
Undefined
⎯
⎯
7
Undefined
EP3 CLR
Initial
Value
Undefined ⎯
Undefined W
Undefined W
Undefined W
Undefined ⎯
Undefined W
Undefined W
W
6
Undefined
EP1 CLR
R/W
⎯
W
5
Description
Reserved
The write value should always be 0.
EP3 Clear
Writing 1 to this bit initializes the endpoint 3 transmit
FIFO buffer.
EP1 Clear
Writing 1 to this bit initializes both sides of the
endpoint 1 receive FIFO buffer.
EP2 Clear
Writing 1 to this bit initializes both sides of the
endpoint 2 transmit FIFO buffer.
Reserved
The write value should always be 0.
EP0o Clear
Writing 1 to this bit initializes the endpoint 0 receive
FIFO buffer.
EP0i Clear
Writing 1 to this bit initializes the endpoint 0 transmit
FIFO buffer.
Undefined
EP2 CLR
W
4
Undefined
⎯
⎯
3
Rev. 2.00 Oct. 21, 2009 Page 981 of 1454
Section 20 USB Function Module (USB)
Undefined
⎯
⎯
2
EP0o CLR
Undefined
W
1
REJ09B0498-0200
Undefined
EP0i CLR
W
0