R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 14

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
6.7
6.8
6.9
Section 7 Interrupt Controller............................................................................ 125
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
Rev. 2.00 Oct. 21, 2009 Page xii of xxxii
Instruction Exception Handling ........................................................................................ 120
6.7.1
6.7.2
6.7.3
Stack Status after Exception Handling ............................................................................. 123
Usage Note ....................................................................................................................... 124
Features............................................................................................................................. 125
Input/Output Pins.............................................................................................................. 127
Register Descriptions........................................................................................................ 127
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
Interrupt Sources............................................................................................................... 143
7.4.1
7.4.2
Interrupt Exception Handling Vector Table...................................................................... 145
Interrupt Control Modes and Interrupt Operation............................................................. 152
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
CPU Priority Control Function Over DTC, DMAC and EXDMAC ................................ 161
Usage Notes ...................................................................................................................... 164
7.8.1
7.8.2
7.8.3
7.8.4
7.8.5
7.8.6
Interrupt Priority Registers A to O, Q, and R
(IPRA to IPRO, IPRQ, and IPRR) .................................................................... 131
Trap Instruction ................................................................................................ 120
Sleep Instruction Exception Handling .............................................................. 121
Exception Handling by Illegal Instruction ........................................................ 122
Interrupt Control Register (INTCR) ................................................................. 128
CPU Priority Control Register (CPUPCR) ....................................................... 129
IRQ Enable Register (IER) ............................................................................... 133
IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 134
IRQ Status Register (ISR)................................................................................. 140
Software Standby Release IRQ Enable Register (SSIER) ................................ 141
External Interrupts ............................................................................................ 143
Internal Interrupts ............................................................................................. 144
Interrupt Control Mode 0.................................................................................. 152
Interrupt Control Mode 2.................................................................................. 154
Interrupt Exception Handling Sequence ........................................................... 156
Interrupt Response Times ................................................................................. 157
DTC and DMAC Activation by Interrupt ......................................................... 158
Conflict between Interrupt Generation and Disabling ...................................... 164
Instructions that Disable Interrupts................................................................... 165
Times when Interrupts are Disabled ................................................................. 165
Interrupts during Execution of EEPMOV Instruction ...................................... 165
Interrupts during Execution of MOVMD and MOVSD Instructions................ 165
Interrupts of Peripheral Modules ...................................................................... 166

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