R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 455

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(5)
Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is
automatically cleared to 0 according to the DMA transfer state by the DMAC.
The conditions for clearing the DTE bit by the DMAC are as follows:
• When the total size of transfers is completed
• When a transfer is completed by a transfer size error interrupt
• When a transfer is completed by a repeat size end interrupt
• When a transfer is completed by an extended repeat area overflow interrupt
• When a transfer is stopped by an NMI interrupt
• When a transfer is stopped by and address error
• Reset state
• Hardware standby mode
• When a transfer is stopped by writing 0 to the DTE bit
Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited
(except for the DTE bit). When changing the register settings after writing 0 to the DTE bit,
confirm that the DTE bit has been cleared to 0.
Figure 10.21 show the procedure for changing the register settings for the channel being
transferred.
Figure 10.21 Procedure for Changing Register Setting For Channel being Transferred
DTE Bit in DMDR
of channel during operation
Changing register settings
Change register settings
Write 0 to DTE bit
End of changing
register settings
Read DTE bit
DTE = 0?
Yes
No
[1]
[2]
[3]
[4]
[1] Write 0 to the DTE bit in DMDR.
[2] Read the DTE bit.
[3] Confirm that DTE = 0. DTE = 1
[4] Write the desired values to the
indicates that DMA is transferring.
registers.
Rev. 2.00 Oct. 21, 2009 Page 421 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200

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