R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 585

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 11.71 Procedure for Clearing Transfer End Interrupt and Restarting Transfer
after BKSZ changed from 1 to 0
Destination address extended
repeat area overflow occurred
repeat area overflow occurred
in the transfer size error state
Activation source occurred
Activation source occurred
Source address extended
[1] Write set values to the registers
[2] Write 1 to the DTE bit in EDMDR to restart
[3] The interrupt handling routine is
End of transfer restart processing
SARIE bit
DARIE bit
TSEIE bit
RPTIE bit
End of interrupt handling routine
Transfer continuation processing
(transfer counter, address registers, etc.)
EXDMA operation. When 1 is written to
the DTE bit, the DTIF or ESIF bit in EDMDR is
automatically cleared to 0 and the interrupt
source is cleared.
ended with an RTE instruction, etc.
(RTE instruction execution)
exception handling routine
Transfer end interrupt of
Change register settings
Write 1 to DTE bit
Figure 11.70 Interrupts and Interrupt Sources
[1]
[2]
[3]
End of transfer restart processing
End of interrupt handling routine
Transfer restart after end of
Clear DTIF or ESIF bit to 0
interrupt handling routine
Change register settings
[4] Write 0 to the DTIF or ESIF bit
[5] After the interrupt handling routine is
[6] Write set values to the registers
[7] Write 1 to the DTE bit in EDMDR
Write 1 to DTE bit
(transfer counter, address registers, etc.).
in EDMDR by first reading 1 from it.
ended with an RTE instruction, etc.,
interrupt masking is cleared.
to restart EXDMA operation.
DTIE bit
DTIF bit
ESIE bit
ESIF bit
Rev. 2.00 Oct. 21, 2009 Page 551 of 1454
Section 11 EXDMA Controller (EXDMAC)
Condition to set DTIF bit to 1: DTCR
is set to 0 and transfer ends.
Condition to set ESIF bit to 1
[4]
[5]
[6]
[7]
REJ09B0498-0200
Transfer
end interrupt
Transfer escape
end interrupt

Related parts for R5F61665N50FPV