R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 825

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4
Figure 15.3 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to 16 bits is possible by writing new output data to NDR before the next
compare match.
15.4.1
If pulse output is enabled, the NDR contents are transferred to PODR and output when the
specified compare match event occurs. Figure 15.4 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
Operation
Output Timing
Figure 15.4 Timing of Transfer and Output of NDR Contents (Example)
Pulse output pin
Pφ
TCNT
NDRH
TGRA
PODRH
PO8 to PO15
Compare match
A signal
Figure 15.3 Schematic Diagram of PPG
Normal output/inverted output
m
N
m
Q
NDER
PODR
Q
Output trigger signal
C
Section 15 Programmable Pulse Generator (PPG)
D
N
n
N + 1
Rev. 2.00 Oct. 21, 2009 Page 791 of 1454
Q
NDR
D
n
n
Internal data bus
REJ09B0498-0200