R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 456

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
(6)
The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0
or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the
DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0
and the transfer is not completed, the ACT bit retains 1.
In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1-
block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to
completion of a 1-block size transfer.
In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE
bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA
transfer.
(7)
When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the
channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an
address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in
operation.
However, when the DMAC is in the module stop state, the ERRF bit is not set to 1 for address
errors or the NMI.
(8)
When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow is
requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a
transfer escape interrupt is requested to the CPU or DTC.
The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus
cycle of the interrupt source is completed.
The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is
resumed by setting the DTE bit to 1 during interrupt handling.
For details on interrupts, see section 10.8, Interrupt Sources.
Rev. 2.00 Oct. 21, 2009 Page 422 of 1454
REJ09B0498-0200
ACT Bit in DMDR
ERRF Bit in DMDR
ESIF Bit in DMDR