R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 330

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Bus Controller (BSC)
Table 9.23 Pin States during DRAM Refresh Cycle
The RAS signal can be delayed for one to three clock cycles by setting bits RCW1 and RCW0 in
REFCR. The pulse width of the RAS signal is changed by bits RLW2 to RLW0 in REFCR. The
settings of bits RCW1, RCW0, and RLW2 to RLW0 are effective only for a refresh cycle. The
precharge time set by bit TPC1 and TPC0 is effective for a refresh cycle.
Figure 9.55 shows timing for setting bits RCW1 and RCW0
Rev. 2.00 Oct. 21, 2009 Page 296 of 1454
REJ09B0498-0200
Pin
A17 to A0
D15 to D0
RAS
LUCAS, LLCAS
WE
AS
RD
BS
RD/WR
RD/WR
LUCAS
(RCW1 = 0, RCW0 = 1, RLW2 = 0, RLW1 = 0, RLW0 = 0)
LLCAS
RAS
Bφ
BS
TR
Figure 9.55 CBR Refresh Timing
p
TR
State
Hold the value of the previous bus cycle
Hi-Z
Used for refresh control
Used for refresh control
High
High
High
High
High
rw
High
High
TR
r
TR
c1
TR
c2