R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 174

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 7 Interrupt Controller
7.3.6
ISR is an IRQ15, IRQ14, and IRQ11 to IRQ0 interrupt request register.
Rev. 2.00 Oct. 21, 2009 Page 140 of 1454
REJ09B0498-0200
Bit
15
14
13, 12
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Notes: 1. Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should
2. Supported only by the H8SX/1665M Group.
IRQ Status Register (ISR)
be used to clear the flag.
Bit Name
IRQ15F
IRQ14F*
IRQ15F
R/(W)*
R/(W)*
IRQ7F
15
0
7
0
1
1
2
IRQ14F*
Initial
Value
0
0
All 0
R/(W)*
R/(W)*
IRQ6F
14
0
6
0
1
1
2
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ5F
13
0
5
0
1
1
1
1
1
Description
[Setting condition]
[Clearing conditions]
[Setting condition]
[Clearing conditions]
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*
R/(W)*
IRQ4F
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQ15F = 1
When IRQ15 interrupt exception handling is
executed while falling-edge sensing is selected
When the interrupt selected by ISCR occurs
Writing 0 after reading IRQ14 = 1
When IRQ14 interrupt exception handling is
executed while falling-edge sensing is selected
12
0
4
0
1
1
IRQ11F
R/(W)*
R/(W)*
IRQ3F
11
0
3
0
1
1
R/(W)*
R/(W)*
IRQ10F
IRQ2F
10
0
2
0
1
1
R/(W)*
R/(W)*
IRQ9F
IRQ1F
9
0
1
0
1
1
R/(W)*
R/(W)*
IRQ8F
IRQ0F
8
0
0
0
1
1

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