R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 917

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
6
5
Bit Name
RDRF
ORER
Initial
Value
0
0
R/W
R/(W)* Receive Data Register Full
R/(W)* Overrun Error
Description
Indicates whether receive data is stored in RDR.
[Setting condition]
•
[Clearing conditions]
•
•
The RDRF flag is not affected and retains its previous
value when the RE bit in SCR is cleared to 0.
Note that when the next serial reception is completed
while the RDRF flag is being set to 1, an overrun error
occurs and the received data is lost.
Indicates that an overrun error has occurred during
reception and the reception ends abnormally.
[Setting condition]
•
[Clearing condition]
•
Section 19 Serial Communication Interface (SCI, IrDA, CRC)
When serial reception ends normally and receive data
is transferred from RSR to RDR
When 0 is written to RDRF after reading RDRF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When an RXI interrupt request is issued allowing
DMAC or DTC to read data from RDR
When the next serial reception is completed while
RDRF = 1
In RDR, receive data prior to an overrun error
occurrence is retained, but data received after the
overrun error occurrence is lost. When the ORER flag
is set to 1, subsequent serial reception cannot be
performed. Note that, in clocked synchronous mode,
serial transmission also cannot continue.
When 0 is written to ORER after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the ORER
flag is not affected and retains its previous value.
Rev. 2.00 Oct. 21, 2009 Page 883 of 1454
REJ09B0498-0200