R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 445

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 DMA Controller (DMAC)
10.5.5
Extended Repeat Area Function
The source and destination address sides can be specified as the extended repeat area. The contents
of the address register repeat addresses within the area specified as the extended repeat area. For
example, to use a ring buffer as the transfer target, the contents of the address register should
return to the start address of the buffer every time the contents reach the end address of the buffer
(overflow on the ring buffer address). This operation can automatically be performed using the
extended repeat area function of the DMAC.
The extended repeat areas can be specified independently to the source address register (DSAR)
and destination address register (DDAR).
The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR.
The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in
DACR. The extended repeat area sizes for each side can be specified independently.
A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested
to the CPU when the contents of the address register reach the end address of the extended repeat
area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in
DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to
stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended
repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an
overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a
target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer.
Rev. 2.00 Oct. 21, 2009 Page 411 of 1454
REJ09B0498-0200