R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1012

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 USB Function Module (USB)
20.3.17 EP1 Receive Data Size Register (EPSZ1)
EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received
from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received
data indicated by this register is the size of the currently selected side (can be read by CPU).
20.3.18 Trigger Register (TRG)
TRG generates one-shot triggers to control the transfer sequence for each endpoint.
Rev. 2.00 Oct. 21, 2009 Page 978 of 1454
REJ09B0498-0200
Bit
7 to 0
Bit
7
6
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
—
Bit Name
⎯
EP3 PKTE
Undefined
—
⎯
⎯
R
7
0
7
EP3 PKTE
Undefined
Initial
Value
All 0
Initial
Value
Undefined ⎯
Undefined W
—
W
R
6
0
6
EP1 RDFN
Undefined
R/W
R
R/W
—
W
R
5
0
5
Description
Number of received bytes for endpoint 1
Description
Reserved
The write value should always be 0.
EP3 Packet Enable
After one packet of data has been written to the
endpoint 3 transmit FIFO buffer, the transmit data is
fixed by writing 1 to this bit.
EP2 PKTE
Undefined
—
W
R
4
0
4
Undefined
—
⎯
⎯
R
3
0
3
EP0s RDFN
Undefined
—
W
R
2
0
2
EP0o RDFN
Undefined
—
W
R
1
0
1
EP0i PKTE
Undefined
—
W
R
0
0
0