R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1048

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 20 USB Function Module (USB)
20.5.6
EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being
aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For
example, even if both FIFOs are empty, it is not possible to perform EP2PKTE at one time after
consecutively writing 128 bytes of data. EP2PKTE must be performed for each 64-byte write.
When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first
IN token, an EP2TR bit interrupt in IFR0 is requested. With this interrupt, 1 is written to the
EP2EMPTY bit in IER0, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs
are empty, and so an EP2 FIFO empty interrupt is generated immediately.
Rev. 2.00 Oct. 21, 2009 Page 1014 of 1454
REJ09B0498-0200
EP2 Bulk-In Transfer (Dual FIFOs)
Data transmission to host
Clear EP2 empty status
(IFR0.EP2 EMPTY = 0)
IN token reception
in EP2 FIFO?
in EP2 FIFO?
Valid data
Space
Figure 20.18 EP2 Bulk-In Transfer Operation
Yes
No
ACK
USB function
No
Yes
NACK
empty status
EMPTY = 1)
(IFR0.EP2
Set EP2
Interrupt request
Interrupt
request
Write one packet of data
(IER0.EP2 EMPTY = 1)
Write 1 to EP2 packet
(TRG.EP2 PKTE = 1)
to EP2 data register
(IFR0.EP2 TR = 0)
Clear EP2 transfer
IFR0.EP2 EMPTY
Enable EP2 FIFO
Application
empty interrupt
request flag
enable bit
(EPDR2)
interrupt