R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 433

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2)
In single address mode, data between an external device and an external memory is directly
transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in
one bus cycle. In this mode, the data bus width must be the same as the data access size. For
details on the data bus width, see section 9, Bus Controller (BSC).
The DMAC accesses an external device as the transfer source or destination by outputting the
strobe signal (DACK) to the external device with DACK and accesses the other transfer target by
outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 10.4
shows an example of a transfer between an external memory and an external device with the
DACK pin. In this example, the external device outputs data on the data bus and the data is written
to the external memory in the same bus cycle.
The transfer direction is decided by the DIRS bit in DACR which specifies an external device with
the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an
external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is
transferred from an external device with the DACK pin to an external memory (DDAR). The
settings of registers which are not used as the transfer source or destination are ignored.
The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The
DACK signal is low active.
The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is
output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is
also output in the idle cycle.
Address B
Address T
Single Address Mode
A
A
Figure 10.3 Operations in Dual Address Mode
Transfer
Address update setting is as follows:
Source address increment
Fixed destination address
Rev. 2.00 Oct. 21, 2009 Page 399 of 1454
Section 10 DMA Controller (DMAC)
REJ09B0498-0200
Address T
B