R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 481

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

DMAC is activated in
transfer size error state
DMAC is activated
after BKSZ bits are
changed from 1 to 0
Extended repeat area
overflow occurs in
source address
Extended repeat area
overflow occurs in
destination address
Figure 10.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source
[1] Specify the values in the registers such as transfer counter and address register.
[2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or
[3] End the interrupt handling routine by the RTE instruction.
[4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit.
[5] Complete the interrupt handling routine and clear the interrupt mask.
[6] Specify the values in the registers such as transfer counter and address register.
[7] Set the DTE bit to 1 to resume DMA operation.
DARIE bit
SARIE bit
RPTIE bit
ESIF bit in DMDR to 0 and an interrupt source is cleared.
TSIE bit
Interrupt handling routine
Registers are specified
ends (RTE instruction
Transfer end interrupt
Consecutive transfer
DTE bit is set to 1
Transfer resume
handling routine
processing end
processing
executed)
Figure 10.39 Interrupt and Interrupt Sources
[1]
[2]
[3]
Interrupt handling routine
interrupt handling routine
DTIF and ESIF bits are
Registers are specified
Transfer resumed after
DTE bit is set to 1
DTIE bit
Transfer resume
Setting condition is satisfied
DTIF bit
processing end
ESIE bit
ESIF bit
cleared to 0
Rev. 2.00 Oct. 21, 2009 Page 447 of 1454
[Setting condition]
When DTCR becomes 0
and transfer ends
ends
Section 10 DMA Controller (DMAC)
[6]
[4]
[5]
[7]
REJ09B0498-0200
Transfer end
interrupt
Transfer escape
end interrupt