R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 579

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3)
In repeat transfer mode, when the RPTIE bit in EDACR is set to 1 and the next transfer request is
generated on completion of a repeat-size transfer, a repeat size end interrupt request is generated.
The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the
ESIF bit in EDMDR is set to 1 at the same time. If the DTE bit is set to 1 in this state, transfer
resumes.
In block transfer or cluster transfer mode, a repeat size end interrupt request can be generated. In
block transfer mode, if the next transfer request is generated at the end of a block-size transfer, a
repeat size end interrupt request is generated. In cluster transfer mode, if the next transfer request
is generated at the end of a cluster-size transfer, a repeat size end interrupt request is generated.
(4)
If an address overflows the extended repeat area when an extended repeat area specification has
been made and the SARIE or DARIE bit in EDACR is set to 1, an extended repeat area overflow
interrupt is requested. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR
is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time.
In dual address mode, if an extended repeat area overflow interrupt is requested during a read
cycle, the following write cycle processing is still executed.
In block transfer mode, if an extended repeat area overflow interrupt is requested during transfer
of a block, transfer continues to the end of the block. Transfer end by means of an extended repeat
area overflow interrupt occurs between block-size transfers.
In cluster transfer mode, if an extended repeat area overflow interrupt is requested during transfer
of a cluster, transfer continues to the end of the cluster. Transfer end by means of an extended
repeat area overflow interrupt occurs between cluster-size transfers.
(5)
When 0 is written to the DTE bit in EDMDR by the CPU, etc., transfer ends after completion of
the EXDMA cycle in which transfer is in progress or a transfer request was accepted.
In block transfer mode, EXDMA transfer ends after completion of one-block-size transfer in
progress.
In cluster transfer mode, EXDMA transfer ends after completion of one-cluster-size transfer in
progress.
Transfer End by Repeat Size End Interrupt
Transfer End by Extended Repeat Area Overflow Interrupt
Transfer End by 0-Write to DTE Bit in EDMDR
Rev. 2.00 Oct. 21, 2009 Page 545 of 1454
Section 11 EXDMA Controller (EXDMAC)
REJ09B0498-0200