R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 785

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Note: This table shows the initial state immediately after a reset. The relative channel priority
(1)
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1
by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is
cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
(2)
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to
1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing
the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel.
(3)
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to
1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by
clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4,
and 5.
Channel Name
3
4
5
Input Capture/Compare Match Interrupt
Overflow Interrupt
Underflow Interrupt
levels can be changed by the interrupt controller.
TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
TGI4A
TGI4B
TCI4V
TCI4U
TGI5A
TGI5B
TCI5V
TCI5U
Interrupt Source
TGRA_3 input capture/compare match
TGRB_3 input capture/compare match
TGRC_3 input capture/compare match
TGRD_3 input capture/compare match
TCNT_3 overflow
TGRA_4 input capture/compare match
TGRB_4 input capture/compare match
TCNT_4 overflow
TCNT_4 underflow
TGRA_5 input capture/compare match
TGRB_5 input capture/compare match
TCNT_5 overflow
TCNT_5 underflow
Interrupt
Flag
TGFA_3
TGFB_3
TGFC_3
TGFD_3
TCFV_3
TGFA_4
TGFB_4
TCFV_4
TCFU_4
TGFA_5
TGFB_5
TCFV_5
TCFU_5
Rev. 2.00 Oct. 21, 2009 Page 751 of 1454
Section 14 16-Bit Timer Pulse Unit (TPU)
DTC
Activation
Possible
Possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Not possible
Possible
Possible
Not possible
Not possible
REJ09B0498-0200
DMAC
Activation
Possible
Not possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible
Possible
Not possible
Not possible
Not possible

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