R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 1291

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
7
6
Bit Name
DPSBY
IOKEEP
Initial
Value
0
0
R/W
R/W
R/W
Module
Deep Software Standby
When the SSBY bit in SBYCR has been set to 1, executing
the SLEEP instruction causes a transition to software
standby mode. At this time, if there is no source to clear
software standby mode and this bit is set to 1, a transition
to deep software standby mode is made.
When deep software standby mode is canceled due to an
interrupt, this bit remains at 1. Write a 0 here to clear it.
Setting of this bit has no effect when the WDT is used in
watchdog timer mode. In this case, executing the SLEEP
instruction always initiates entry to sleep mode or all-
module-clock-stop mode. Be sure to clear this bit to 0 when
setting the SLPIE bit to 1.
I/O Port Retention
In deep software standby mode, the ports retain the states
that were held in software standby mode. This bit specifies
whether or not the state that has been held in deep
software standby mode is retained after exit from deep
software standby mode.
In operation in external extended mode, however, the
address bus, bus control signals (CS0, AS, RD, HWR, and
LWR), and data bus are set to the initial state upon exit
from deep software standby mode.
SSBY
0
1
1
IOKEEP
0
1
DPSBY
x
0
1
Pin State
The retained port states are released
simultaneously with exit from deep
software standby mode.
The retained port states are released
when a 0 is written to this bit following exit
from deep software standby mode.
Rev. 2.00 Oct. 21, 2009 Page 1257 of 1454
Entry to
Enters sleep mode after
execution of a SLEEP
instruction.
Enters software standby mode
after execution of a SLEEP
instruction.
Enters deep software standby
mode after execution of a
SLEEP instruction.
Section 28 Power-Down Modes
REJ09B0498-0200