R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 115

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
3.2.2
SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets
external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Bit
15
14
13
12
11
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Note: * The initial value depends on the startup mode.
Bit Name
MACS
FETCHMD 0
System Control Register (SYSCR)
R/W
R/W
15
1
7
0
Initial
Value
1
1
0
1
R/W
R/W
14
1
6
0
R/W
R/W
R/W
R/W
R/W
R/W
MACS
R/W
R/W
13
0
5
0
Descriptions
Reserved
These bits are always read as 1. The write value should
always be 1.
MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction is non-saturation operation
1: MAC instruction is saturation operation
Reserved
This bit is always read as 1. The write value should
always be 1.
Instruction Fetch Mode Select
This LSI can prefetch an instruction in units of 16 bits or
32 bits. Select the bus width for instruction fetch
depending on the used memory for the storage of
programs.
0: 32-bit mode
1: 16-bit mode
R/W
R/W
12
1
4
0
FETCHMD
R/W
R/W
11
0
3
0
Rev. 2.00 Oct. 21, 2009 Page 81 of 1454
Undefined*
R/W
Section 3 MCU Operating Modes
10
R
2
0
Undefined*
DTCMD
EXPE
R/W
R/W
9
1
1
REJ09B0498-0200
RAME
R/W
R/W
8
1
0
1

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