R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 27

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.11 CRC Operation Circuit ..................................................................................................... 954
Section 20 USB Function Module (USB)..........................................................961
20.1
20.2
20.3
19.10.4 Receive Error Flags and Transmit Operations
19.10.5 Relation between Writing to TDR and TDRE Flag .......................................... 950
19.10.6 Restrictions on Using DTC or DMAC.............................................................. 950
19.10.7 SCI Operations during Power-Down State ....................................................... 951
19.11.1 Features............................................................................................................. 954
19.11.2 Register Descriptions ........................................................................................ 955
19.11.3 CRC Operation Circuit Operation..................................................................... 957
19.11.4 Note on CRC Operation Circuit........................................................................ 960
Features............................................................................................................................. 961
Input/Output Pins.............................................................................................................. 962
Register Descriptions........................................................................................................ 963
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
20.3.7
20.3.8
20.3.9
20.3.10 EP0i Data Register (EPDR0i) ........................................................................... 974
20.3.11 EP0o Data Register (EPDR0o) ......................................................................... 975
20.3.12 EP0s Data Register (EPDR0s) .......................................................................... 975
20.3.13 EP1 Data Register (EPDR1) ............................................................................. 976
20.3.14 EP2 Data Register (EPDR2) ............................................................................. 976
20.3.15 EP3 Data Register (EPDR3) ............................................................................. 977
20.3.16 EP0o Receive Data Size Register (EPSZ0o) .................................................... 977
20.3.17 EP1 Receive Data Size Register (EPSZ1) ........................................................ 978
20.3.18 Trigger Register (TRG)..................................................................................... 978
20.3.19 Data Status Register (DASTS).......................................................................... 980
20.3.20 FIFO Clear Register (FCLR) ............................................................................ 981
20.3.21 DMA Transfer Setting Register (DMA) ........................................................... 982
20.3.22 Endpoint Stall Register (EPSTL)...................................................................... 985
20.3.23 Configuration Value Register (CVR) ............................................................... 986
20.3.24 Control Register (CTLR) .................................................................................. 986
20.3.25 Endpoint Information Register (EPIR) ............................................................. 988
(Clocked Synchronous Mode Only).................................................................. 949
Interrupt Flag Register 0 (IFR0) ....................................................................... 964
Interrupt Flag Register 1 (IFR1) ....................................................................... 966
Interrupt Flag Register 2 (IFR2) ....................................................................... 967
Interrupt Select Register 0 (ISR0)..................................................................... 969
Interrupt Select Register 1 (ISR1)..................................................................... 970
Interrupt Select Register 2 (ISR2)..................................................................... 971
Interrupt Enable Register 0 (IER0) ................................................................... 972
Interrupt Enable Register 1 (IER1) ................................................................... 973
Interrupt Enable Register 2 (IER2) ................................................................... 973
Rev. 2.00 Oct. 21, 2009 Page xxv of xxxii

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