R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 974

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Serial Communication Interface (SCI, IrDA, CRC)
19.7.7
Data reception in smart card interface mode is similar to that in normal serial communication
interface mode. Figure 19.32 shows the data re-transfer operation during reception.
1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI
2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1.
3. If no parity error is detected, the PER bit in SSR is not set to 1.
4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is
Figure 19.33 shows a sample flowchart for reception. All the processing steps are automatically
performed using an RXI interrupt request to activate the DTC or DMAC. In reception, setting the
RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This
activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI
interrupt request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag
is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs during
reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI)
request is generated and the error flag must be cleared. If an error occurs, the DTC or DMAC is
not activated and receive data is skipped, therefore, the number of bytes of receive data specified
in the DTC or DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in
reception, receive data is transferred to RDR, thus allowing the data to be read.
Note: For operations in block transfer mode, see section 19.4, Operation in Asynchronous Mode.
Rev. 2.00 Oct. 21, 2009 Page 940 of 1454
REJ09B0498-0200
interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the
next parity bit is sampled.
set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1.
RDRF
PER
Serial Data Reception (Except in Block Transfer Mode)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 19.32 Data Re-Transfer Operation in SCI Reception Mode
nth transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransfer frame
(DE)
[4]
[3]
Ds D0 D1 D2 D3 D4
transfer frame
(n + 1) th