R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 910

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 Serial Communication Interface (SCI, IrDA, CRC)
19.3.6
SCR is a register that enables/disables the following SCI transfer operations and interrupt requests,
and selects the transfer clock source. For details on interrupt requests, see section 19.9, Interrupt
Sources. Some bits in SCR have different functions in normal mode and smart card interface
mode.
• When SMIF in SCMR = 0
• When SMIF in SCMR = 1
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Rev. 2.00 Oct. 21, 2009 Page 876 of 1454
REJ09B0498-0200
Bit
7
6
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit Name
TIE
RIE
Serial Control Register (SCR)
R/W
R/W
TIE
TIE
7
0
7
0
Initial
Value
0
0
R/W
R/W
RIE
RIE
6
0
6
0
R/W
R/W
R/W
R/W
R/W
TE
TE
5
0
5
0
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
A TXI interrupt request can be cancelled by reading 1
from the TDRE flag and then clearing the flag to 0, or by
clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI and ERI interrupt requests can be cancelled by
reading 1 from the RDRF, FER, PER, or ORER flag and
then clearing the flag to 0, or by clearing the RIE bit to 0.
R/W
R/W
RE
RE
4
0
4
0
MPIE
MPIE
R/W
R/W
3
0
3
0
TEIE
TEIE
R/W
R/W
2
0
2
0
CKE1
CKE1
R/W
R/W
1
0
1
0
CKE0
CKE0
R/W
R/W
0
0
0
0