R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 178

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Interrupt Controller
Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, P5ICR, and P6ICR register
settings, and does not change regardless of the output setting. However, when a pin is used as an
external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing
the corresponding DDR bit to 0.
A block diagram of interrupts IRQn is shown in figure 7.2.
When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn
should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn
to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed
when the corresponding input signal IRQn is set to high before the interrupt handling begins.
7.4.2
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
• The interrupt priority can be set by means of IPR.
• The DTC and DMAC can be activated by a TPU, SCI, or other interrupt request.
• The priority levels of DTC and DMAC activation can be controlled by the DTC and DMAC
Rev. 2.00 Oct. 21, 2009 Page 144 of 1454
REJ09B0498-0200
IRQn input
[Legend]
n = 11 to 0
and enable bits that enable or disable these interrupts. They can be controlled independently.
When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
priority control functions.
Corresponding bit
Internal Interrupts
Input buffer
in ICR
Figure 7.2 Block Diagram of Interrupts IRQn
IRQnSF, IRQnSR
detection circuit
Edge/level
Clear signal
R
S
IRQnF
Q
IRQnE
IRQn interrupt request