R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 164

• Manufacturer Part Number: R5F61665N50FPV
• Description: MCU FLASH 512K ROM 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61665N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Interrupt Controller
Note:
Rev. 2.00 Oct. 21, 2009 Page 130 of 1454
REJ09B0498-0200
Bit
3
2
1
0
*
Bit Name
IPSETE
CPUP2
CPUP1
CPUP0
When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits
cannot be modified.
Initial
Value
0
0
0
0
R/W
R/W
R/(W)*
R/(W)*
R/(W)*
Description
Interrupt Priority Set Enable
Controls the function which automatically assigns the
interrupt priority level of the CPU. Setting this bit to 1
automatically sets bits CPUP2 to CPUP0 by the CPU
interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR).
0: Bits CPUP2 to CPUP0 are not updated automatically
1: The interrupt mask bit value is reflected in bits
CPU Priority Level 2 to 0
These bits set the CPU priority level. When the
CPUPCE is set to 1, the CPU priority control function
over the DTC, DMAC and EXDMAC becomes valid and
the priority of CPU processing is assigned in
accordance with the settings of bits CPUP2 to CPUP0.
000: Priority level 0 (lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (highest)
CPUP2 to CPUP0