R5F61665N50FPV Renesas Electronics America, R5F61665N50FPV Datasheet - Page 71

MCU FLASH 512K ROM 144-LQFP

R5F61665N50FPV

Manufacturer Part Number
R5F61665N50FPV
Description
MCU FLASH 512K ROM 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61665N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61665N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• Stack Structure
2.2.4
The program area is extended to 4 Gbytes as compared with that in advanced mode.
• Address Space
• Extended Registers (En)
• Instruction Set
• Exception Vector Table and Memory Indirect Branch Addresses
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
The maximum address space of 4 Gbytes can be linearly accessed.
The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit
segments of 32-bit registers or address registers.
All instructions and addressing modes can be used.
In maximum mode, the top area starting at H'00000000 is allocated to the exception vector
table. One branch address is stored per 32 bits. The structure of the exception vector table is
shown in figure 2.6.
Maximum Mode
SP
Notes: 1.
Figure 2.5 Stack Structure (Middle and Advanced Modes)
2.
3.
(a) Subroutine Branch
When EXR is not used it is not stored on the stack.
SP when EXR is not used.
Ignored on return.
Reserved
(24 bits)
PC
(SP
SP
*
2
)
(b) Exception Handling
Rev. 2.00 Oct. 21, 2009 Page 37 of 1454
Reserved*
(24 bits)
EXR*
CCR
PC
1
1
, *
3
REJ09B0498-0200
Section 2 CPU

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